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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 august 1993 integrated circuits SAA2520 stereo filter and codec for mpeg layer 1 audio applications
august 1993 2 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 features stereo filtering and codec functions in a single chip mpeg coded interface filtered data interface baseband audio data interface lt interface to microcontroller clock generator low operating voltage capability. general description the SAA2520 performs the sub-band filtering and audio frame codec functions to provide efficient audio compression/decompression for mpeg (11172-3) layer1 applications. it is capable of functioning as a stand-alone decoder but requires the addition of an adaptive masking threshold processor (saa2521) in order to function as a highly efficient encoder. ordering information note 1. sot205-1; 1996 august 26. extended type number package pins pin position material code SAA2520gp (1) 44 qfp plastic sot205ag fig.1 block diagram. handbook, full pagewidth mlb125 microprocessor interface & control baseband serial interface filtered data interface freset 15 fdir syncdai ltcnt1 ltena ltclk ltdata pwrdwn reset urda ltcnt0 14 13 36 35 34 33 32 22 29 6 18 17 16 fdaf fdac fsync 5,37 20 19 21 sws scl sda stereo sub-band filter processor codec sub-band serial interface clock generator 1 fs256 7 11 sbdir sbef 8 9 10 12 2 3 4 sbda sbcl sbws sbmclk mutedac deemdac attdac 38 39 40 41 42 43 28,44 clk22 x22in x24in clk24 x22out x24out v dd SAA2520 v ss
august 1993 3 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 fs256 mutedac deemdac attdac v ss urda sbdir sbda sbcl sbws sbef v dd x24out x24in x22out x22in clk24 clk22 v ss ltcnt1 ltcnt0 ltena pwrdwn sda sws scl fdac fdaf fsync freset fdir syncdai sbmclk dsc4 dsc3 dsc2 dsc1 dsc0 reset t1 t0 ltdata ltclk v dd SAA2520 mlb126 fig.3 mpeg decoder system data flow diagram. handbook, full pagewidth mlb127 audio amplifier microcontroller dac SAA2520 digital audio interface control system micro interface power down reset mpeg source mpeg interface
august 1993 4 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 pinning symbol pin description type fs256 1 (filtered)-i 2 s clock; 256 sample frequency. 12 ma 3-state output + cmos input with pull-down i/o mutedac 2 dac control/output expander o deemdac 3 dac control/output expander o attdac 4 dac control/output expander o v ss 5 supply ground (0 v) urda 6 unreliable drive processing data; cmos level i sbdir 7 sub-band i 2 s direction: (swbs, sbcl, sbda); cmos level i sbda 8 sub-band i 2 s data; 4 ma, 3-state output + cmos input with pull-down i/o sbcl 9 sub-band i 2 s bit clock; 4 ma, 3-state output + cmos input with pull-down i/o sbws 10 sub-band i 2 s word select; 4 ma, 3-state output + cmos input with pull-down i/o sbef 11 sub-band i 2 s byte error ?ag; cmos level i sbmclk 12 sub-band i 2 s clock, 6.144 mhz locked to fs256; 8 ma, 3-state output + cmos input with pull-down o syncdai 13 dai synchronization pulse o fdir 14 (filtered)-i 2 s direction: (fdac, fdaf, sda); o freset 15 reset signal for saa2521 o fsync 16 filtered-i 2 s sync signal for saa2521 o fdaf 17 filtered-i 2 s sub-band ?lter data; 4 ma, 3-state output + cmos input with pull-down i/o fdac 18 filtered-i 2 s sub-band codec data; 4 ma, 3-state output + cmos input with pull-down i/o scl 19 i 2 s bit clock; 4 ma, 3-state output + cmos input with pull-down i/o sws 20 i 2 s-word select; 4 ma, 3-state output + cmos input with pull-down i/o sda 21 i 2 s baseband data ?lter; 4 ma, 3-state output + cmos input with pull-down i/o pwrdwn 22 power-down mode; cmos level i dsc4 23 test pin dsc3 24 test pin dsc2 25 test pin dsc1 26 test pin dsc0 27 test pin v dd 28 positive supply voltage (+5 v) reset 29 system reset; cmos level with pull-down and hysteresis i t1 30 test pin; do not connect t0 31 test pin; do not connect ltdata 32 lt interface data; 4 ma, 3-state output + cmos input with pull-down i/o ltclk 33 lt interface bit clock; cmos level i
august 1993 5 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 ltena 34 lt interface enable; cmos level i ltcnt0 35 lt interface control; cmos level i ltcnt1 36 lt interface control; cmos level i v ss 37 supply ground (0 v) clk22 38 22.5792 mhz buffered output o clk24 39 24.576 mhz buffered output o x22in 40 22.5792 mhz crystal input i x22out 41 22.5792 mhz crystal output o x24in 42 24.576 mhz crystal input i x24out 43 24.576 mhz crystal output o v dd 44 positive supply voltage (+5 v) symbol pin description type
august 1993 6 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.4 encoding mode. handbook, full pagewidth mlb128 formatter mpeg output data sub - band samples allocation & scale factor information table scaling & quantization sync and coding information from saa2521 allocation information and scale factor indices quantized samples sub-band filter base band samples fig.5 decoding mode. handbook, full pagewidth mlb129 de formatter mpeg input data scale factor scale factor array & allocation dequantization control multiply allocation sync/coding quantized samples sub-band samples output control sub-band filter base band samples
august 1993 7 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 functional description coding system mpeg coding achieves highly efficient digital encoding of audio signals by using an algorithm based on the characteristics of the human auditory system. the broad-band audio signal is split into 32 sub-band signals during encoding. for each of the sub-band signals the masking threshold is calculated. the samples of the sub-bands are incorporated in the signal with an accuracy that is determined by the signal to masking threshold ratio for that sub-band. during decoding, the sub-band signals are reconstructed and combined into a broadband audio signal. the integrated filter processor performs the splitting (encoding) and joining (decoding) including the corresponding formatting functions. for encoding, a saa2521 is necessary to calculate the masking threshold and required accuracy of the sub-band samples. encoding (see fig.4) an encoding algorithm table is used during the coding process but, due to the adaptive allocation functions of the saa2521, this may change with every frame. the table is therefore calculated for each frame by the saa2521 and then transferred to the SAA2520. a frame contains 2 384 samples of left and right audio data. this results in 12 samples per sub-band (32 sub-bands). the samples of the greatest amplitude are used to determine the scale factor for a given sub-band. all samples are then scaled to represent a fraction of the greatest amplitude. once scaled, the samples are quantized to reduce the number of bits to correspond with the allocation table as calculated by the saa2521. synchronization and coding information data is then added to result in a fully encoded mpeg signal. decoding (see fig.5) all essential information (synchronization, system information, scale factors and encoded sub-band samples) are conveyed by incoming data. decoding is repeated for every frame. after sync and coding information, allocation data and the scale factors are used to correctly fill the scale factor array. this is followed by a process of multiplication to provide de-quantization and de-scaling of the samples. the decoded sub-band samples, which are represented in 24-bit two's complement notation, are processed by the sub-band filters and reconstituted into a single digital audio signal. reset reset must be active under the following conditions: 1. from system power-up until clk24 has executed more than 24 clock cycles. 2. from the falling edge of pwrdwn for a period equivalent to 24 cycles of clk24 + oscillator start-up time. this is typically >1 ms, however, this value is crystal dependent. pwrdwn a high input applied to this pin will halt all internally generated clock signals. as a result, chip activity will halt completely with outputs frozen in the state which was current at the time of pwrdwn activation. the bi-directional outputs: ltdata, fdac, fdaf, sda, sbws, sbcl and sbda will be 3-stated. crystal oscillators a 24.576 mhz crystal together with some external components form the 24.576 mhz oscillator (pins 42 and 43). similarly a 22.5792 mhz oscillator (pins 40 and 41) is formed by similar peripheral components together with an appropriate crystal (see fig.6). the component values shown apply only to crystals from the philips 4322 156 series which exhibit an equivalent series resistance of 40 w .
august 1993 8 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.6 crystal oscillator components. component values apply only to crystals from the philips 4322 156 series. handbook, full pagewidth SAA2520 40 41 42 43 r1 1 m w 22.5792 mhz x1 r2 1 k w c2 33 pf c1 33 pf r4 1 m w 24.576 mhz x2 r3 1 k w c3 33 pf c4 33 pf x22in x22out x24in x24out mlb130 fig.7 transfer of sda data (standard i 2 s default format). mla923 - 2 left 32 bits right 13 bits 1 000 1 7 1 6 1 5 1 4 msb lsb 1 7 1 6 1 5 1 4 msb channel sws scl sda bit : 210 18 bits
august 1993 9 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.8 transfer of sda data (alternative format). mla924 - 2 left 32 bits right 14 bits 000 1 7 1 6 1 5 1 4 msb lsb 1 7 1 6 1 5 1 4 msb channel sws scl sda bit : 210 18 bits 1 3 fig.9 transfer of fdaf and fdac (filtered) data. mla925 - 2 left 32 bits right 7 bits 1 0 2 0 1 0 0 2 3 2 2 2 1 2 0 msb lsb 2 3 2 2 2 1 2 0 msb channel sws scl fdac/ fdaf bit :
august 1993 10 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 baseband interface signals the interface between the SAA2520 and the baseband input/output circuitry consists of the following signals: sws bi-directional word (channel) select fs scl bi-directional bit clock 64fs sda bi-directional baseband data fdir output decoding mode (direction control) fig.10 sws related to phase of fsync. mbc148 - 1 channel sws lrllllll rrrrrr fsync sub-band 31 0 1 31 0 1 the sws signal indicates the channel of the sample signal (either left or right) and is equal to the sampling frequency fs. operating at a frequency of 64 times that is used for sampling, the bit clock dictates that each sws period contains 64 sda data bits. of these, a maximum of 36 are used to transfer data (samples may have a length up to 18-bits). samples are transferred most significant bit first. both sws and sda change state at the negative edge of scl. this baseband data is transferred between the SAA2520 and the input/output using either standard i 2 s (default) or the alternative format shown in fig.8.
august 1993 11 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 interface between SAA2520 and saa2521 consists of the following signals: f iltered -i 2 s interface sws bi-directional word select (common to i 2 s) fs scl bi-directional bit clock (common to i 2 s) 64fs fdac bi-directional codec data fdaf bi-directional ?lter data fsync output synchronization fs/32 filtered data is transferred between SAA2520 filter/codec functions and the saa2521 using the format shown in fig.9. the frequency of the sws signal is equal to the sample frequency fs and the bit clock scl is 64 times the sample frequency. each period of sws contains 64 data-bits, 48 of which are used to transfer data. the half period in which sws is low is used to transfer the information of the left channel while the following half period during which sws is high carries the data of the right channel. the 24-bit samples are transferred most significant bit first. this bit is transferred in the bit clock period with a 1-bit delay following the change in sws. both sws and fdaf/fdac change state at the negative edge of scl. the saa2521 may be synchronized to the sub-band codec using the fsync signal, which defines the sws period in which the samples of sub-band 0 (containing the lowest frequency components) are transferred (see fig.10). saa2521 and input / output mode control the operation of saa2521 and the input/output circuitry is controlled by three signals shown in table 1. freset and syncdai are given whenever: - fs256, scl and sws outputs switch between high and low impedance - fs256 frequency is changed (12.288/11.2896/8.192 mhz) - fdir is switching - bit rate is changing - system reset is active mpeg c oded i nterface the interface that carries the mpeg coded signal uses the following signals: the mpeg i 2 s interface the sbmclk signal is the main frequency from which other clock signals are derived. in encode mode this division is performed internally. in decode mode the external source should provide sbws and sbcl. the frequency of the signal is equal to 1/32nd of the bit rate. the frequency of the bit clock sbcl is twice that of the bit rate. some examples of the frequencies are given in table 2. sbws bi-directional word selection sbcl bi-directional bit clock sbda bi-directional sub-band coded data sbef input error signal operation is further controlled by: sbdir input direction of data ?ow urda input unreliable encoded data signal
august 1993 12 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 table 1 saa2521 input/output control. table 2 frequency examples. freset output request a general reset of saa2521 fdir output '1' for decoding and '0' for encoding mode (common to i 2 s) syncdai output pulse for synchronization of digital input/output (tda1315) bit rate (k bits/s) sbws frequency (khz) sbcl frequency (khz) 384 12 768 256 8 512 192 6 384 128 4 256 e ncode m ode the following modes are supported: stereo or 2-channel mono with allowable bit rates of 384, 256, 192 and 128 kbits/s; audio sampling frequencies of 48, 44.1 and 32 khz. d ecode mode the following modes are supported: stereo and joint stereo, 2-channel mono and 1-channel mono with allowable bit rates in the range 448 to 32 k bits/s; audio sampling frequencies of 48, 44.1 and 32 khz.
august 1993 13 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.11 filtered i 2 s interface timing (master mode - fs256, scl and sws are input). mea642 - 3 sws, sda, fdaf, fdac, fsync output t t fh fl t t d1 t d1 t sl t sh t c fs256 t h2 t d2 scl sda, fdaf, fdac input t h1 t su notes to fig.11 t fs256 cycle time (f s = 48 khz) fs256 cycle time (f s = 44.1 khz) fs256 cycle time (f s = 32 khz) 81.4 ns nominal 88.6 ns nominal 122.1 ns nominal t c scl cycle time 4t ns nominal t fh fs256 high time (f s = 48 khz) fs256 high time (f s = 44.1 khz) fs256 high time (f s = 32 khz) 3 35 ns 3 38 ns 3 35 ns t fl fs256 low time (f s = 48 khz) fs256 low time (f s = 44.1 khz) fs256 low time (f s = 32 khz) 3 35 ns 3 38 ns 3 75 ns t sh scl high time 3 2t - 20 ns t sl scl low time 3 2t - 20 ns t s sda, fdaf, fdac input set-up before fs256 high 3 20 ns t h1 sda, fdaf, fdac input hold after fs256 high 3 30 ns t h2 sda, fdaf, fdac output hold after fs256 high 0 ns t d1, 2 fs256 high to scl, sws, sda, fdaf, fdac output valid 50 ns
august 1993 14 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.12 filtered i 2 s interface timing (slave mode - fs256, scl and sws are input). mea644 - 3 t fl t fh t c t sh t sl t h1 t d t su t h2 fs256 scl sda, fdaf, fdac, fsync output sws, sda, fdaf, fdac input t notes to fig.12 t fh fs256 high time 3 35 ns t fl fs256 low time 3 35 ns t sh scl high time 3 t + 35 ns t sl scl low time 3 t + 35 ns t h1 sda, fdaf, fdac output hold after scl high 3 2t - 15 ns t d scl high to sda, fdaf fdac output valid 3t + 60 ns t s sda, fdaf, fdac input valid after scl high 3 20 ns t h2 sda, fdaf, fdac input hold after scl high 3 t + 20 ns
august 1993 15 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.13 mode switch timing. mea646 - 1 fdir sda fdaf fdac t d3 t d2 syncdai freset t d0 t sh t d1 high z t d4 high z t d6 high z high z t d7 fdaf fdac high z sws fs256 scl t d8 t d9 sws fs256 scl high z t d5 sda notes to fig.13 t do freset high to syncdai high 3 300 ns t sh syncdai high time 3 1280 ns t d1 syncdai low to freset low 3 790 ns t d2 fdir hold to freset high 20 ns t d3 freset high to fdir valid 20 ns t d4 sda change to high impedance after freset high 3 0 ns 170 ns t d5 sda remains high impedance after freset low 3 0 ns 170 ns t d6 fdaf, fdac change to high impedance after freset high 20 ns t d7 fdaf, fdac remain high impedance
august 1993 16 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 notes to fig.13 after freset high 3 460 ns t d8 fs256, sws, scl change to high impedance before syncdai high 3 140 ns t d9 fs256, sws, scl remain high impedance after syncdai high 3 140 ns fig.14 transferring mpeg data to and from the SAA2520. 32 bits 15 bits 1 1 0 1 1 1 2 0 0 0 1 0 2 0 3 1 6 1 7 1 8 sbws sbcl sbda bit : 2 0 2 1 mea649 - 2 msb sbef lsb msb byte 0 byte 1 byte 2 1 9 2 2 1 1 3 1 4 1 5
august 1993 17 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 mpeg coded interface (sub-band i 2 s) the mpeg coded data is transferred to and from the SAA2520 using the format shown in fig.14. each period of sbws contains 64 data bits, 32 of which are used to convey data. the half-period during which sbws is logic 0 is used to transfer the first 16-bits (0 to 15) of a sub-band slot. the remaining half-period during which sbws is logic 1 carries the remaining 16-bits (16 to 31). thus one period of sbws corresponds with one slot of the sub-band signal. bits 0 and 16 are transferred in the bit clock period, one bit-time after the change in sbws. both sbws and sbda change state during the negative edge of sbcl. in decode mode a byte error flag sbef is also transferred. this occurs approximately in the middle of the corresponding byte (byte 0 = bits 0 to 7, byte 1 = bits 8 to 15 etc). encoding mode sbcl, sbws and sbda are generated by the SAA2520. however, if the sbdir signal is logic 1, the output buffers are not enabled and these signals do not appear on the pins. this mode is available to permit a change of operating mode whilst the bus signals are driven from an external source. decoding mode sbcl, sbws and sbda are generated by an external source. table 3 contains a summary of the source signals in the various modes. table 3 modes and source signals. notes 1. during encoding the sbef signal is dont care. 2. incoming data is not decoded. the SAA2520 operates in the encoding mode and the data does not enter the interface. 3. operation is undefined. the SAA2520 is in decoding mode whilst the sbws, sbcl and sbda output drivers are enabled. source of: mode fdir sbdir sbws sbcl sbda sbef sbmclk encode 0 0 int int int ---- int note 1 encode 0 1 ext ext ext ---- int note 2 decode 1 0 int int int ext int note 3 decode 1 1 ext ext ext ext int
august 1993 18 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.15 sub-band i 2 s interface timing (master mode - sbcl, sbws and sbda are output). mea645 - 2 t ml t mh t sc t cl t ch sbmclk sbcl sbws sbda t d2 t d1 t s notes to fig.15 t sbmclk cycle time 120 to 205 ns (163 ns nominal) t mh sbmclk high time 3 35 ns t ml sbmclk low time 3 75 ns t c sbcl cycle time (384 kb/s) sbcl cycle time (256 kb/s) sbcl cycle time (192 kb/s) sbcl cycle time (128 kb/s) 8t ns nominal 12t ns nominal 16t ns nominal 24t ns nominal t ch sbcl high time (384 kb/s) sbcl high time (256 kb/s) sbcl high time (192 kb/s) sbcl high time (128 kb/s) 3 4t - 20 ns 3 6t - 20 ns 3 8t - 20 ns 3 12t - 20 ns t cl sbcl low time (384 kb/s) sbcl low time (256 k/bs) sbcl low time (192 kb/s) sbcl low time (128 kb/s) 3 4t - 20 ns 3 6t - 20 ns 3 8t - 20 ns 3 12t - 20 ns t d1 sbws, sbda hold to sbcl low 20 ns t d2 sbcl low to sbws, sbda valid 20 ns
august 1993 19 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.16 sub-band i 2 s interface timing (slave mode - sbcl, sbws and sbda are input). mea648 - 2 t sc t cl t ch sbda sbcl sbws sbda t h1 t su1 t su2 t h2 sbef 0 1 2 3 4 5 6 7 8 9 10 11 12 sbef sbcl sbws notes to fig.16 t c sbcl cycle time (see note 1) 6.86t to 96t ns (8t ns nominal) t ch sbcl high time 3 t + 30 ns t cl sbcl low time 3 t + 30 ns t s1 sbws, sbda input set-up before sbcl high 3 t + 30 ns t h1 sbws, sbda input hold after sbcl high 3 30 ns t s2 sbcl high to sbef valid t - 30 ns t h2 sbef hold after sbcl high note 1: minimum at bit rate = 448 kb/s nominal at bit rate = 384 kb/s maximum at bit rate = 32 kb/s 3 2t- 30 ns
august 1993 20 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 notes to fig.17 t d1 sbdir high to sbcl, sbws, sbda high impedance 50 ns t d2 sbcl, sbws, sbda after sbdir low high impedance 3 240 ns fig.17 sub-band i 2 s mode switch timing. mea647 - 1 high z t d1 sbcl sbws sbda high z t d2 sbdir
august 1993 21 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 microcontroller interface the SAA2520 has an interface connection to the serial interface of a microcontroller. the following signals are used: ltclk input bit clock ltdata bi-directional serial data ltcnt0 input control line 0 ltcnt1 input control line 1 ltena input enable the SAA2520 microcontroller interface is enabled only if ltena (pin 34) is logic 1. information to or from the SAA2520 is conveyed in serial 8 or 16-bit units, whilst the type of information is controlled by ltcnt0 (pin 35) and ltcnt1 (pin 36). a transfer commences when the microcontroller sets the control lines to the correct combination for the required action. ltena is set to logic 1. the SAA2520 determines its required action and prepares to transfer data. when the microcontroller supplies the ltclk, data is transferred to or from the SAA2520 in units of 8-bits. 16-bit transfers are conveyed as two 8-bit units during which ltena remains high. during the transfer of 8-bit units, the least significant bit is first to be transferred. when 16-bit units are transferred the most significant byte is sent first. e xtended s ettings (ltcnt1 = 0, ltcnt0 = 0) four information bits together with four address bits are transferred in this mode. the order in which the bits appear on the interface is: d0..d1..d2..d3..a0..a1..a2..a3 table 4 extended settings. table 5 extended settings. note if not used for dac control, the mutedac, attdac and deemdac can be used as general purpose output expanders. bit a3 bit a2 bit a1 bit a0 description 0 0 0 0 codec external settings (see table 5) 0 0 0 1 filter settings (see note 1) 0 0 1 0 not used .. .. .. .. .. 1 1 1 1 not used bit designation default function d0 mutedac 1 connected to dac mute input d1 attdac 0 connected to dac attenuation input d2 deemdac 0 emphasis control for dac circuit d3 holdclkok 0 selects clkok hold mode
august 1993 22 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 bits d0 to d3 are copied directly to the corresponding output pins/mode flip-flop. for holdclkok = logic 1. when clkok drops it will remain low until set by an encode/decode mode, sample frequency, external 256fs or bit rate index change. note 1. when d0 = logic 1 (default) i 2 s mode is selected. for d0 = logic 0 the alternative mode is selected. the setting of d0 remains dormant until activated by the occurrence of freset. a llocation /s cale f actor i nformation (ltcnt1 = logic 0, ltcnt0 = logic 1) for encoding, the allocation and scale factor arrays can be filled using this mode. to completely fill the allocation array 16 complete transfers of 16-bits are required. after the first transfer of allocation information a check must be made to determine when the SAA2520 is ready to receive the remaining information. this will ensure synchronization with the internal program of the SAA2520. transfer of the allocation information is completed by sending the internal settings. this is then followed by the scale factor information. in the event that only internal settings information is sent, then a default allocation of logic 0 will be assigned to all sub-bands. if in addition no internal settings are sent then the previous settings remain valid. the allocation information is transferred in 4-bit units. each of these units contains the number of bits allocated to the sub-band, minus 1, except in the case of a logic 0 value, which indicates that no bits are allocated to that sub-band. scale factor information is transferred in units of 8-bits, containing the 6-bit scale factor which is extended to 8-bits by adding two logic 0s at the most significant end. in the case of stereo encoding the channels are indicated by l (left) and r (right). this changes to i and ii in the case of 2 channel mono encoding. table 6 allocation information format. table 7 scalefactor information format. msb bits lsb channel sub-band b15 - b14 - b13 - b12 l or i 0 .. 30 (even) b11 - b10 - b9 - b8 r or ii 0 .. 30 (even) b7 - b6 - b5 - b4 l or i 1 .. 31 (odd) b3 - b2 - b1 - b0 r or ii 1 .. 31 (odd) msb bits lsb channel sub-band b15 ................ b8 l or i 0 .. 31 b7 ................ b0 r or ii 0 .. 31
august 1993 23 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 i nternal s ettings (ltcnt1 = logic 1, ltnct 0 = logic 0) the operation of the codec is controlled by the bits transferred in this mode. table 8 internal settings (ltcnt1 = logic 1, ltnct 0 = logic 0). table 9 internal settings (ltcnt1 = logic 1, ltcnt0 = logic 0). msb lsb name function valid in s15 ... s12 bit rate index bit rate indication encode s11 ... s10 sample frequency 44.1, 48 or 32 khz indication encode s9 decode 1 = decode; 0 = encode encode/decode s8 ext 256fs 1 = external; 0 = internal 256fs encode/decode s7 2-channel mono 1 = 2-ch mono; 0 = stereo encode s6 mute 1 = mute; 0 = no mute encode/decode s5 not used s4 ch1 1 = ch1; 0 = ch2 decode s3 ... s2 tr0 to tr1 transparent bits encode s1 ... s0 emphasis emphasis indication encode msb lsb bit rate 1100 384 kbits/s default value 1000 256 kbits/s 0110 192 kbits/s 0100 128 kbits/s the bit rate index indicates the bit rate of the encoded signal and is only effective in the encode mode. the decode bit determines the operation mode of the SAA2520. the default value is logic 1 (decoding mode). ext 256fs in the encoding mode determines whether or not the SAA2520 is master or slave of the filtered-i 2 s interface (default is logic 0, master mode). 2ch mono is used in the encoding mode to determine whether the sub-band signal is generated as a stereo or 2-channel mono signal. default value is logic 0. mute is used in both the encoding and decoding modes to mute the information to or from the filtered-i 2 s interface (the default value is logic 0). ch1 is utilized in the decoding mode to select one of the 2-channel mono signals to be decoded (default is i - channel 1). a value of 0 results in channel 2 being decoded). the transparent bits are copied in the sub-band signal, default is 00. the information from s15 to s10, s7 and s3 to s0 will be copied into the sub-band signal.
august 1993 24 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 table 10 sample frequency indication. table 11 emphasis indication. s tatus (ltcnt = logic 1, ltnct0 = logic 1) table 12 status information 16-bit units. msb lsb sample frequency 0 0 44.1 khz default value 0 1 48 khz 1 0 32 khz 1 1 not used msb lsb emphasis 0 0 no emphasis default value 0 1 50/15 m s 1 0 reserved 1 1 ccitt j.17 before sending internal settings the microcontroller should check whether or not the SAA2520 is ready-to-receive. however, this does not apply for the transfer of internal settings to end a transfer of allocation information. msb lsb name function valid in t15 ... t12 bit rate index bit rate indication encode/decode t11 ... t10 sample frequency 44.1, 48 or 32 khz indication encode/decode t9 ready-to-receive 1 = ready; 0 = not ready encode/decode t8 not used t7 t6 mode sub-band signal mode indication encode/decode t5 sync synchronization indication decode t4 clkok 1 = o.k.; 0 = not o.k. encode/decode t3 t2 tr0 to tr1 transparent bits encode/decode t1 ... t0 emphasis emphasis indication encode/decode the bit rate index indicates the bit rate of the sub-band signal in units of 32 kbits/s. bit rate index 0000 indicates the free format condition. bit rate 1111 is illegal and should not be found. the coding of the sample frequency indication is equal to the one in the internal settings.
august 1993 25 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 table 13 mode identi?cation. msb lsb mode output 0 0 stereo l and r 0 1 joint stereo l and r 1 0 2 channel mono i or ii as selected 1 1 1 channel mono mono; no selection ready-to-receive indicates whether the SAA2520 is ready to receive allocation, scale factor or internal setting transfers. this should be checked in order to synchronize the transfer of such information. in 2 channel mono decode mode the selected samples are transferred to both output channels. the same occurs with all samples in 1-channel mono decode mode. in both of these instances the l and r filter output channels are identical. in decode mode the sync bit is logic 0 when the SAA2520 is unable to decode the sub-band frames. this will occur in the following situations: with the loss of synchronisation when in correct allocation information is received for two or more subsequent frames (sbef was high). when the urda input pin is high in these situations the SAA2520 data output will be muted. the sync bit will return to logic 1 as soon as the decoder is resynchronized to the incoming sub-band data. clkok indicates whether the 256fs clock corresponds to specified sample frequency. the clkok bit is set to logic 1 after a change in sample frequency, operation mode or ext256fs setting. it drops to logic 0 as soon as the 256fs clock deviates from the nominal frequency by more than approximately 0.2%. return to logic 1 will only occur automatically when the extended setting clkok-hold-mode is logic 0. the transparent bits are copied from the mpeg coded signal. the emphasis indication is as defined in the internal settings. it can be used to apply the correct de-emphasis. note: the two bytes of the status are 'sampled' at different moments so the information may not result from the same sub-band frame.
august 1993 26 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.18 transfer of data on SAA2520 microcontroller interface. handbook, full pagewidth mlb131 01234567 ltena ltclk ltdata lsb msb ltcnt0/1 fig.19 the ltena line must return to logic 0 between information transfers. handbook, full pagewidth mlb132 ltena ltclkc 16 bits allocation / scale factor information 16 bits allocation / scale factor information
august 1993 27 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fig.20 order of settings and status bits on the SAA2520 microcontroller interface. handbook, full pagewidth mlb133 ltena ltclk ltdata bit : 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 15 ltcnt0/1 fig.21 16-bit transfers. t d6 delay ltclk high to ltdata valid output for bit 0 in 16-bit transfers handbook, full pagewidth mlb134 ltena ltclk ltena must remain high d6 t ltcnt0/1 ltdata output 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
august 1993 28 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 notes to fig.22 t el ltena low time 3 190 ns t ch ltclk high time 3 190 ns t cl ltclk low time 3 190 ns t d1 ltena high to ltclk high 3 190 ns t d2 ltena high to ltdata output low impedance 3 0 ns t d3 ltena high to ltdata output valid 380 ns t d4 ltena low to ltdata high impedance 50 ns t h4 ltena hold after ltclk high 3 355 ns t d5 ltclk high to ltena high 3 190 ns t d6 ltclk high to ltdata output valid for bit 0 (see fig.21) for ?rst bit in the second 8-bit unit 355 ns 520 ns t s1 ltcnt0/1 set-up before ltena high 3 190 ns t h1 ltcnt0/1 hold after ltena high 3 190 ns t s2 ltdata set-up before ltclk high 3 190 ns t h2 ltdata input hold after ltclk high 3 30 ns t h3 ltdata output hold after ltclk high 3 145 ns t h4 ltena hold after ltclk high 3 355 ns fig.22 microcontroller interface timing. handbook, full pagewidth mlb135 t h1 t s1 t el t d1 t cl t ch t d5 t s2 t h2 t h3 t d6 t d3 t d2 ltena ltclk ltcdata input ltcdata output t d4 t h4 hiz hiz ltcnt0 ltcnt1
august 1993 29 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 limiting values in accordance with the absolute maximum system (iec 134). notes 1. input voltage should not exceed 6.5 v unless otherwise specified 2. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor 3. equivalent to discharging a 200 pf capacitor through a 0 w series resistor. dc characteristics t amb = - 40 to 85 c; v dd = 3.8 to 5.5 v unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.5 6.5 v v i input voltage note 1 - 0.5 v dd + 0.5 v i ss supply current from v ss - 160 ma i dd supply current in v dd - 160 ma i i input current - 10 10 ma i o output current - 20 20 ma p tot total power dissipation - 880 mw t stg storage temperature range - 55 150 c t amb operating ambient temperature range - 40 85 c v es1 electrostatic handling note 2 - 1500 1500 v v es2 electrostatic handling note 3 - 70 70 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage range 3.8 5.0 5.5 v i dd operating current v dd = 5 v (note 1) - 82 110 ma i dd operating current v dd = 3.8 v (note 1) - 58 80 ma inputs urda, sbdir, sbef, ltclk, ltcnt0, ltnct1, x22in, x24in v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v - i i input current v i = 0 v; t amb = 25 c -- 10 m a +i i input current v i = 5.5 v; t amb = 25 c -- 10 m a inputs pwrdwn, ltena v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v +i i input current v i = v dd ; t amb = 25 c 40 - 250 m a
august 1993 30 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 note 1. for load impedances representative of the application. input reset v tlh positive-going threshold -- 0.8v dd v v thl negative-going threshold 0.2v dd -- v v hys hystersis (v tlh - v thl ) - 1.5 - v +i i input current v i = v dd ; t amb = 25 c 40 - 250 m a outputs mutedac, deemdac, attdac, syncdai, fdir, freset, fsync, clk22 v oh high level output voltage +i o = 2 ma v dd - 0.5 -- v v ol low level output voltage - i o = 2 ma -- 0.4 v outputs clk24 v oh high level output voltage +i o = 8 ma v dd - 0.5 -- v v ol low level output voltage - i o = 8 ma -- 0.4 v inputs/outputs sbda, sbcl, sbws, fdaf, fdac, scl, sws, sda, ltdata v oh high level output voltage +i o = 2 ma v dd - 0.5 -- v v ol low level output voltage - i o = 2 ma -- 0.4 v outputs sbda, sbcl, sbws, fdaf, fdac, scl, sws, sda, ltdata in 3-state v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v i i input current v i = v dd ; t amb = 25 c 40 - 250 m a input/output sbmclk v oh high level output voltage +i o = 8 ma v dd - 0.5 -- v v ol low level output voltage - i o = 8 ma -- 0.4 v output sbmclk in 3-state v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v i i input current v i = v dd ; t amb = 25 c 40 - 250 m a input/output fs256 v oh high level output voltage +i o = 12 ma v dd - 0.5 -- v v ol low level output voltage - i o = 12 ma -- 0.4 v output fs256 in 3-state v ih high level input voltage 0.7v dd -- v v il low level input voltage -- 0.3v dd v i i input current v i = v dd ; t amb = 25 c 40 - 250 m a symbol parameter conditions min. typ. max. unit
august 1993 31 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 ac characteristics t amb = - 40 to 85 c; v dd = 3.8 to 5.5 v unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit inputs c i input capacitance -- 10 pf x24in and x22in f crystal frequency at x22out, clk22 note 1 21 22.5792 24 mhz f crystal frequency at x24out, clk24 note 1 23 24.576 26 mhz gm mutual conductance 100 khz 1.5 -- ma/v a v small signal gain a v = gm.r o 3.5 -- v/v c fb feedback capacitance -- 5pf c o output capacitance -- 10 pf outputs c o output capacitance -- 10 pf inputs urda, reset, ltdata, ltclk, ltena, ltcnt0, ltcnt1 t su setup time to x24in 15 -- ns t hd hold time to x24in 60 -- ns outputs ltdata, mutedac, deemdac, attdac, syncdai, fdir, freset t d propagation delay from x24in -- 80 ns inputs fdaf, fdac, sda, scl, sws t su setup time to fs256 15 -- ns t hd hold time to fs256 25 -- ns outputs fdaf, fdac, sda, scl, sws, fsync t d propagation delay from fs256 -- 50 ns inputs sbda, sbcl, sbws, urda, sbdir, sbef t su setup time to sbmclk 15 -- ns t hd hold time to sbmclk 25 -- ns outputs sbda, sbcl, sbws t d propagation delay from sbmclk -- 50 ns fs256 t fs256 cycle time f s = 48 khz - 81.4 - ns t fs256 cycle time f s = 44.1 khz - 88.6 - ns t fs256 cycle time f s = 32 khz - 122.1 - ns t c scl cycle time - 4t - ns
august 1993 32 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 fs256 master mode (fs256,scl and sws are output) t fh fs256 high time f s = 48 khz 35 -- ns t fh fs256 high time f s = 44.1 khz 38 -- ns t fh fs256 high time f s = 32 khz 75 -- ns t fl fs256 low time f s = 48 khz 35 -- ns t fl fs256 low time f s = 44.1 khz 38 -- ns t fl fs256 low time f s = 32 khz 75 -- ns t sh scl high time 2t-20 -- ns t sl scl low time 2t-20 -- ns t s sda, fdaf, fdac input setup time before fs256 high 20 -- ns t h1 sda, fdaf, fdac input hold time after fs256 high 30 -- ns t h2 sda, fdaf, fdac output hold time after fs256 high 0 -- ns t d1,2 fs256 high-to scl, sws, sda, fdaf, fdac output valid -- 50 ns fs256 slave mode (fs256, scl and sws are input) t fh fs256 high time 35 -- ns t fl fs256 low time 35 -- ns t sh scl high time t+35 -- ns t sl scl low time t+35 -- ns t h1 sda, fdaf, fdac output hold time after scl high 2t-15 -- ns t d scl high-to sda, fdaf, fdac output valid -- 3t+60 ns t s sda, fdaf, fdac input valid after scl high 20 -- ns t h2 sda, fdaf, fdac input hold time after scl high t+20 -- ns sbmclk t sbmclk cycle time 120 163 205 ns t mh sbmclk high time 35 -- ns t ml sbmclk low time 75 -- ns symbol parameter conditions min. typ. max. unit
august 1993 33 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 notes 1. % deviation from nominal frequency must be the same for x24, x22, and fs256 inputs to within 0.2% 2. minimum value for bit rate = 448 kb/s typical value for bit rate = 384 kb/s maximum value for bit rate = 32 kb/s sbmclk master mode (sbcl, sbws and sbda are output) t c sbcl cycle time 384 kb/s - 8t - ns t c sbcl cycle time 256 kb/s - 12t - ns t c sbcl cycle time 192 kb/s - 16t - ns t c sbcl cycle time 128 kb/s - 24t - ns t ch sbcl high time 384 kb/s 4t - 20 -- ns t ch sbcl high time 256 kb/s 6t - 20 -- ns t ch sbcl high time 192 kb/s 8t - 20 -- ns t ch sbcl high time 128 kb/s 12t - 20 -- ns t cl sbcl low time 384 kb/s 4t - 20 -- ns t cl sbcl low time 256 kb/s 6t - 20 -- ns t cl sbcl low time 192 kb/s 8t - 20 -- ns t cl sbcl low time 128 kb/s 12t - 20 -- ns t d1 sbws, sbda hold to sbcl low 20 -- ns t d2 sbws, sbda valid after sbcl 0 -- 20 ns sbmclk slave mode (sbcl, sbws and sbda are input) t c sbcl cycle time note 2 6.86t 8t 96t ns t ch sbcl high time t + 30 -- ns t cl sbcl low time t + 30 -- ns t s1 sbws, sbda setup time before sbcl high t + 30 -- ns t h1 sbws, sbda hold time after sbcl high 30 -- ns t s2 delay before sbef valid after sbcl high -- t - 30 ns t h2 sbef hold time after sbcl high 2t - 30 -- ns symbol parameter conditions min. typ. max. unit
august 1993 34 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 19.2 18.2 2.4 1.8 7 0 o o 0.15 2.35 0.1 0.3 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2.0 1.2 sot205-1 95-02-04 97-08-01 d (1) (1) (1) 14.1 13.9 h d 19.2 18.2 e z 2.4 1.8 d b p e q e a 1 a l p detail x l (a ) 3 b 11 y c d h b p e h a 2 v m b d z d a z e e v m a x 1 44 34 33 23 22 12 133e01a pin 1 index w m w m 0 5 10 mm scale qfp44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm sot205-1 a max. 2.60
august 1993 35 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
august 1993 36 philips semiconductors preliminary speci?cation stereo ?lter and codec for mpeg layer 1 audio applications SAA2520 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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